It is common in the electronic arts to use buses to interconnect various portions of an electronic system. In general a bus comprises one or more conductors (electrical or optical) along which digital signals are carried from one part of an electronic system to another, according to specific protocols defined by the system and bus architecture. For example, in computers, avionics, and other computer based instrumentation and control systems, a “back-plane” bus is often used.
FIG. 1 is a simplified electrical schematic diagram of a prior art electronic system 10 employing a back-plane bus 12. System 10 has a single board computer (SBC) 14, communication interface16, I/O control 18, power supply 20, and mass memory 22. These elements, enclosed within outline 24, and referred to collectively as electronic sub-system 24, are coupled to back-plane bus 12 via leads or buses 13, 15, 17, 19, 21, respectively. Back-plane bus 12 allows the various elements of electronic sub-system 24 to communicate with each other and with various interface units 26-1 through 26-N, designated as I/O-1 through I/O-N. I/O units 26-1 through 26-N are coupled to peripheral subsystems 1 through N (identified as 36-1 through 36-N), via leads or buses 37-1 through 37-N.
FIG. 2 is a simplified schematic diagram of further electronic system 30 according to the prior art. System 30 has electronic system portion 24 with analogous elements 12, 14, 16, 20, 22 and coupling buses or leads 13, 15, 17, 19, 21 equivalent to those shown FIG. 1 and identified by like reference numbers. However, system 30 communicates with I/O's 32-1 through 32-N via controller 18′ over serial bus leads 31-1 through 31-N respectively, rather than via parallel bus 12. I/O's 32-1 through 32-N in turn communicate with subsystems 36-1 through 36-N over bus or leads 37-1 through 37-N, respectively.
The arrangements of FIG. 1 and FIG. 2 differ in that communication with I/O-1 to I/O-N and thus to subsystem-1 to subsystem-N, occurs in a different manner. Back-plane bus 12 of system 10 which carries signals to I/O-1 to I/O-N in FIG. 1 is generally a parallel bus, that is, each digit in a digital word flowing along the bus is generally carried by a separate lead or wire in the bus. For example, if the digital word used by system 10 has 16 bits, there will ordinarily be at least that many leads in bus 12. An advantage of prior art system 10 is that the parallel back-plane bus arrangement is comparatively fast, since digital data is carried in parallel on bus 12 to I/O-1 to I/O-N. However, a disadvantage of the arrangement of system 10 of FIG. 1 is that an electrical or logical failure in any of I/O-1 to I/O-N can shut down the entire system if it disables bus 12. For example, suppose that the Jth I/O port I/O-J, where 1≦J≦N, suffers a logical or electrical failure and begins to “babble”, that is send unwanted information to bus 12 when it should otherwise be silent. This has the effect of potentially tying up bus 12 so that sub-system 24 is prevented from communicating with any other I/O and vice versa.
In contrast, while system 30 of FIG. 2 uses back-plane bus 12 within sub-system 24, it communicates with peripherals I/O-1 to I/O-N via serial leads 31-1 through 31-N. With serial leads or serial busses, fewer leads are employed and the bits in a digital word are typically sent sequentially in time, one after the other along the same wires or fibers, rather than all at the same time on multiple parallel leads as in system 10. The arrangement of FIG. 2 has the advantage that a logical or electrical fault in any of I/O-1 through I/O-N does not disrupt communication to the remainder of I/O-1 through I/O-N. All other things being equal, this substantially increases the electronic communication reliability within system 30 as compared to system 10. The price paid for improved reliability is generally poorer speed performance. All other things being equal, sending the bits of a digital word along a single lead or lead pair, one bit after the other, takes longer than sending the bits in parallel along a parallel (e.g., back-plane) bus. Another disadvantage of the serial bus is that there are generally not as many choices of I/O devices available for serial bus systems.
FIG. 3 is a simplified electrical schematic block diagram of prior art electronic system 40 showing a protective bus isolation arrangement utilizing custom isolator and I/O components 50-1 through 50-N. Electronic controller 24 comprising elements 14, 16, 18, 20, 22 of FIGS. 1–2 communicates with back-plane bus 12 over bus 23 equivalent to buses 13, 15, 17, 19, 21 of FIGS. 1–2. Back-plane bus 12 is a parallel bus to facilitate high-speed operation. Back-plane bus 12 communicates with interface elements 50, (e.g., 50-1 through 50-N) via buses 47 (e.g., buses 47-1 through 47-N) respectively. Elements 50 comprise a bus isolator 501 (e.g., 501-1 through 501-N) and custom I/O 502 (e.g., 502-1 through 502-N). Bus isolators 501 pass any messages originated by sub-system 24 through I/O devices 502 to subsystems 36 (e.g., 36-1 through 36-N), respectively, and pass legitimate responses therefrom back to sub-system 24 while preventing failure of one or more peripherals 36 from tying up bus 12. While this arrangement works to some extent, it generally requires that I/O units 502 be custom designed for each subsystem 36, bus isolator 501 and bus 12. There is little or no interchangeability, that is, peripheral subsystems 36-1 through 36-N cannot, in general, be swapped among interface units 50. Custom designed isolator units 501 are often required. The need for custom designs significantly increases the initial and ongoing cost of overall system 40. Most importantly, advantage cannot easily be taken of the many commercially available I/O elements and peripheral subsystems that do not provide for bus isolation. In addition, failures within an individual isolator and/or its associated custom I/O can still prevent bus 12 from communicating with other peripherals or preclude other peripherals from communicating with bus 12. Thus, prior art system 40 is only a partial and undesirably costly solution to the problem of providing high speed and fault-tolerant bus-peripheral interfaces.
Accordingly, it is desirable to provide a bus communication interface and method with the speed attributes resembling a parallel bus arrangement and the bus reliability usually found in serial bus arrangements. In addition, it is desirable to implement the bus interface in such a way that industry standard elements, boards, subsystems and peripherals may be employed in so far as possible, rather than having to custom design each I/O for different peripherals. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.